0 Preface The video surveillance system has been widely used in daily life, and its stable and reliable work has become a necessary condition to ensure the normal operation of people's production and life. Reliable and fast acquisition of input, codec, and processing transmissions is a key point in the design of video processing equipment. This article describes a digital video unit based on DaVinci technology. The unit mainly completes the intelligent collection and processing function of the video information and the integrated image processing function. 1 video unit composition and hardware design The video unit uses T MS320DM365 as the core processor chip, and designs video buffering and video decoding functions centering on TMS320DM365. The hardware of the unit mainly includes DaVinci processor chip (TMS320DM365, hereinafter referred to as DM365), video decoder chip (TV P5158), DDR2 SDRAM, FLASH, EN C28J60 Ethernet controller, power management chip and so on. The block diagram of the video unit is shown in Figure 1. This article mainly introduces the video capture input part, the external memory part, the Ethernet part and the video output part. The DM365 is highly integrated with a wide range of components, including H.264, MPEG 4, MPEG 2, MJPEG and VC1 codecs that meet production requirements, integrated image signal processing (ISP) solutions for intelligent video processing functions and a range of boards. Load peripherals, etc., to reduce system cost. Figure 1 video unit block diagram The working principle of the video unit is as follows: T VP5158 The video decoding chip performs analog/digital conversion on the analog video signal transmitted from the CCD camera to become a digital video signal conforming to the IT UR BT . 656 or YU V standard; then the digital video signal is transmitted and arrived. The front end of the Finch processor's video processing subsystem is preprocessed and sent to the back end of the video processing subsystem. The back end of the video processing subsystem encodes the digital video signal and outputs it directly to the display terminal. The ARM side of the DM365 acts primarily as a controller to control the video decoder chip and peripheral interface chip. 1. 1 video capture input design The camera transmits the acquired analog video signal to the TV P5158 video decoder. The T VP5158 device is a 4-channel, high quality NTSC/PAL video decoder that digitally encodes all baseband analog video formats into digital video signal outputs. Each channel of the encoder contains a 10-bit 27 MSPS analog-to-digital converter. The TVP5158 supports NTSC (J, M, 4. 43) and PAL (B, D, G, H, I, M, N, Nc, 60) standard video input simultaneously. Composite video input is supported for each video decode channel. The TV P5158 output port supports 8-bit ITU R BT.656 and 16-bit 4 2 2 YUV formats. The TVP5158 video decoder then transmits the decoded signal to the DM365's Video Processing Front End (VPFE). The T VP5158's highly flexible video output seamless interface to the DM365 eliminates the need for an external FPGA. The interface block diagram of TVP5158 and DM365 is shown in Figure 2. Figure 2 T VP5158 and DM365 interface block diagram The TVP5158 outputs 8-bit ITU RBT.656 and 16-bit 4:2:2 YUV format video. DM365 supports ITU BT. 601/BT . 656/ BT . 1120 digital YCbCr 4 : 2 : 2 ( 8 b / 16 b ) format video, so DM365 in this system uses YCbCr 4:2: 2 8-bit IT UR BT. 656 Video capture mode, the system does not require an external line/field sync signal. The DVO pin of the T VP5158 is connected to the YIN pin of the DM365 for data transfer. 1. 2 external memory design In this unit, the external memory selected is a DDR2 SDRAM chip and a NAND FLASH chip. In this unit, Winbond Electronics' 1 GB DDR2 SDRAM is used as the main memory, model W971GG6IB. The interface block diagram of DM365 and W971GG6IB is shown in Figure 3. CLK and When selected Figure 3 DM365 and W971GG6IB interface block diagram The NAND FLASH selected in the unit is Samsung's K9F2808U0C, which is a 132 MB flash memory with a memory capacity of 16M 8 b capacity and 4 MB spare capacity. The memory array contains 1,024 individually erasable blocks, each of which contains 16KB. The eight I/O pins of the K9F2808U0C are address multiplexed, which reduces the number of pins and facilitates system upgrade. The flash power supply is 3.3 V. The interface block diagram of DM365 and K9F2808U0C is shown in Figure 4. Figure 4 DM365 and K9F2808U0C interface block diagram In Figure 4, I/O0 ~ I/O7 are data input/output pins that are connected to the EM D[ 0: 7] pins for data transfer. The I/O pins are used to input commands, addresses, and data, and are also used to output data during a read operation. 1. 3 Ethernet design The DM365 communicates with the network via the EN C28J60 Ethernet controller. The interface block diagram is shown in Figure 5. Figure 5 DM 365 and ENC28J60 interface block diagram The EN C28J60 Ethernet Controller is a product from Microchip Technology Inc. for thin embedded network applications. The SPI interface of the DM365 is connected to the SPI interface of the ENC28J60 chip. 1. 4 video output design The LCD display is connected to the video processing back end. The block diagram of the video output section is shown in Figure 6. Figure 6 video output block diagram The main function of the OSD module is to capture and mix video data as well as display/bitmap data and transfer them to the Video Encoder (VENC) in YCbCr format. Video and display data are read from external DDR2/mDDR memory. 2 Conclusion The design uses DM365 video processing chip, making full use of its peripheral interface features, and selects some peripheral interface chips to meet the functions of intelligent video processing.
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It is a clock signal pin through which the chip clock is input. 
Latch for row address, 
Latch for column address, 
For write enable, these three pins specify the input command. 
When high, all external commands are disabled; 
External group selection is also available. A0~ A12 are the address bus, the row address in the chip is A0~A12, the column address is A0~A9, and A10 is the automatic pre-charge flag. Because the unit uses a 1 GB DDR2 SDRAM, the BA0 and BA1 pins are selected to select the eight groups on the chip. DQ0~ DQ15 are bidirectional data bus pins that support 16-bit wide data transfers. When DDR DQ S is written, the data is output to the chip; when DDR DQ S is read, the data of the chip is input to the DM365. DDR DQS1 is used for DDRDQ [15: 8] and DDR DQS0 is used for DDR DQ [7: 0]. LDQS is connected to DDR DQS0, LDQS corresponds to data on DQ0~DQ7; U DQS is connected to DDR DQ S1, and UDQS corresponds to data on DQ8 ~ DQ15. LDQS and UDQS are low and high data strobes, respectively. 
It is only used when different data strobe modes are enabled by the EMR control bits. 
The pin is connected to the EM CE0 pin for chip select function. 
The pin is connected to the EM OE pin to control the serial data output. 
The pin is connected to the EM WE pin and controls the writing to the I/O port. Commands, addresses, and data are locked on the rising edge of the WE pulse. R/B is the output pin, connected to the EM WAIT pin, which indicates the state of the device operation. When low, it indicates that a program, erase or random read operation is in progress, and returns to high after the end. Level status. 
For the chip select input pin, SCK is the clock input pin and SI is the data input pin. Two network transformers are also required between the EN C28J60 chip and the RJ 45 interface. Connect a 1:1 pulse transformer dedicated to 10BA SE T operation on the differential receive pin ( T PIN+ / T PIN- ); connect a center tap on the differential transmit pin ( T POUT + / TPOUT - ) 1:1 pulse transformer. The transformer acts as a level shifter and electrical isolation. 
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Design of digital video monitoring unit
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